Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In
نویسندگان
چکیده
منابع مشابه
Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency
Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2009
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2008.2006679